FT61E043-RBFT61F043-RB

•Reduced instruction set architecture
•8-layer hardware stack x12bit
•2T or 4T instruction cycle
•4Kx14b program storage space
i. Automatic checksum verification of program storage space
ii. Configurable, User Option
•256x8b data EEPROM
i. Data EEPROM in-application programming
ii. Configurable, Factory Option
•High endurance EEPROM
Program and data EEPROM can withstand 1 million write operations
i. EEPROM retention time > 40 years
•256x8b SRAM
•Built-in 10-bit ADC, supports 8 channels (7 external channels + 1 internal 1/4VDD channel)
i. Optional reference voltage: external Vref, VDD, internal 2V/3V
ii. Configurable, Factory Option
•Low voltage reset LVR:
i. 2.0/2.2/2.5/2.8/3.1/3.6/4.1V
•Low voltage detection LVD:
i. 2.0/2.4/2.8/3.0/3.6/4.0V
•3 pairs of USB charging ports:
i. Dedicated charging port DC+/DCii. Charging downstream ports DA+/DA-, DB+/DBiii. Support QC2.0 and QC3.0 as well as Apple and Samsung devices
iv. Charge up to two devices at the same time
v. Integrated D2I module
•Up to 18 general IOs, 20 chip pins
i. All IOs with independent pull-up control
ii. 4 IOs with independent pull-down control
•Falling edge interrupt, RA0-RA7
•Support in-system programming ICSP
•Support online debugging, 3 hardware breakpoints
•Program space protection
•Operating voltage range: 2.0V- 5.5V
•Maximum clock operating frequency: 16MHz
i. FSYS=8MHz(2T mode): 2.0V-5.5V
ii. FSYS=16MHz(2T mode): 2.7V-5.5V